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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 259.65+2.3%Jan 23 9:30 AM EST
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To: Scumbria who wrote (28591)2/15/2001 2:19:22 PM
From: combjellyRead Replies (1) of 275872
 
"It is a mistake to use an onboard memory controller, because it ties the chip to a particular type and speed of DRAM"

This is my feeling also. If the north bridge has an eDRAM cache like the (maybe never seeing the light of day) Micron chipsets, then you pretty much have the best of both worlds. That would also allow you to decouple the FSB from the memory bus and reduce the need for a larger L2 cache on the processor, raising it's yields and possibly it's binsplits. If you use LDT, then you could even have multiple north bridges for those cost-no-object, high memory bandwidth applications.
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