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To: Rob Young who wrote (128417)2/27/2001 4:39:23 PM
From: Tenchusatsu  Read Replies (1) of 186894
 
Rob, <How do you build a single server (not multiple systems) with 256 CPUs and a Terabyte of memory that scales?>

Simple. You chain a bunch of multi-CPU nodes together using a custom-designed interconnect. This is how Bull, Fujitsu, Hitachi, IBM's Numa-Q division (formerly Sequent here in Oregon), NEC, and Unisys plan on doing up to 64-way Merced/McKinley systems and beyond.

It's the economics of using a high-volume, high-performance processor, adding your own special sauce (the custom-designed interconnect), and releasing super-scale systems for a fraction of the cost that the competition sees.

<Hint: cache coherence is a problem beyond a certain point.>

Yeah, as if cache coherence wasn't a problem for "simple" 4-way and 8-way SMP systems.

I personally wonder if you even realize the scope of the cache-coherency problem in super-scale systems. It goes way beyond the scope of the petty debate over McKinley vs. EV7 vs. Power4.

Tenchusatsu
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