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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 243.98

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To: survivin who wrote (29827)	2/28/2001 8:43:20 AM
From: Dan3	Read Replies (3) of 275872

Re: Intel set to use PC1600, skip PC2100 until Brookdale P4's QDR bus and asynchronous memory must be a pretty tough nut to crack. Does anyone know what kind of control lines are associated with that bus? Tenchusatsu? I think they're just sending two control signals (top and bottom of the wave) for each 4 data bits. There is no shared bus clock or control line to keep the other two bits coherent. Interfacing to an asynchronous memory bus would likely cause some bits to arrive a few ns early and others a few ns late. Without a control line to enable early or late latching of the data, there would likely be lost data. If they can get their QDR bus up to 133MHZ the clocks at both ends should be enough to let it work OK with PC2100, PC1066 (or interleaved PC133, for that matter). Until then, they're probably better off accepting the modestly lower data rate. OTOH, not shipping at least one data corrupting chipset for P4 would be quite a break with recent Intel tradition - do they want to be that radical? :-) Regards, Dan

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