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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 204.26

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To: Paul Engel who wrote (30289)	3/5/2001 7:59:17 AM
From: Dan3	Read Replies (1) of 275872

Re: A large L2 cache provides enormous system throughput improvements in SMP systems The benefits of a larger cache taper off as cache size increases. Intel's chips are limited to caching 12 pages per LSB, while AMD's chips can cache 20. Since all processes will normally start off with an LSB of 0x000, Intel processors can start thrashing the cache with as few as 12 active processes regardless of cache size, while AMD processors will always support a minimum of 20. The basic design of the Athlon core and cache architecture are more suited to server work than Intel's PIII/P4 architecture. Itanium actually reduces the set associativity from 12 to 10! Which may be one of the reasons why Itanium has been a disappointment, so far. While AMD SMP may never come (I've stopped waiting), if it does ever arrive, it may substantially outperform Xeon in application spaces with many threads. Dan

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