Computing Pioneer Challenges the Clock nytimes.com
Meanwhile, an old topic hits the NYT. Ivan Sutherland is pushing asynchronous logic. Making some rather bold claims, too. You ought to recognize a few names here.
The tiny community of asynchronous logic proponents is made up of
small academic and corporate research teams like Mr. Sutherland's and
several small start-up companies. They say that today's conventional chip
design process will soon reach its practical limits as processors achieve
greater and greater speeds. Among other drawbacks, the current
approach often leaves designers grappling with timing glitches that are
maddeningly difficult to debug.
"You solve a problem at one point in a chip, and it creates problems in
other places that are almost impossible to find," said Wesley Clark, a
computer designer and industry pioneer who has consulted with Mr.
Sutherland's team at Sun Microsystems Laboratories. "It adds
acre-engineer years to the design problem," he said, referring to the need
of chip companies to add another "acre" of engineers to solve a problem.
Some researchers have been intrigued by the possibilities of the
asynchronous approach to computing since the 1950's and 60's, when
the concept was pioneered by John von Neumann at the Institute for
Advanced Study in Princeton, N.J., and by David Muller at the
University of Illinois.
But it has been a largely quixotic quest, and today there are only a
handful of examples of asynchronous designs that work. . . .
Additionally, some longtime computer designers are beginning to use
asynchronous logic to solve thorny problems. Chuck Seitz, an influential
designer of parallel supercomputers at the California Institute of
Technology, is now chief executive of Myricom, a maker of
interconnection systems used to create clusters of I.B.M., Silicon
Graphics and Hewlett-Packard computers. Myricom is now using
asynchronous circuitry where conventional clocked-circuitry would be
unworkable because of the varying clock speeds of the disparate
machines.
He notes that in a complicated modern computer chip as much as 15
percent of the circuitry is devoted to distributing the clock signal and as
much as 20 percent of the power is consumed by the clock.
"Ivan has done excellent work," said Mr. Seitz, who has read the papers
prepared by the Sun research group. Still, he notes that the conventional
design techniques used by circuit designers today will be hard to dislodge
in favor of an unproven approach.
Moreover, some of the nation's best computer designers are outright
skeptics about asynchronous logic. Gordon Bell, the designer of Digital
Equipment's VAX computer architecture in the early 1970's, said that he
was doubtful whether asynchronous logic would ever achieve a following
outside of the research community.
Mr. Bell, who is now a senior researcher at Microsoft, said he had tried
to persuade Mr. Sutherland to enter into a wager over whether
asynchronous designs would be widely adopted but that the two men had
not yet agreed on the terms of the bet.
"I wonder if he's found some new magic potion," Mr. Bell said.
Mr. Sutherland, in fact, says a new magic is precisely what he has found.
He draws an analogy to the first steel bridges, which were built like stone
bridges, with arches. It took some time, he said, for designers to
recognize the possibilities of the suspension bridge — a form impossible
to create with stone alone but which was perfectly suited to the
properties of steel.
The same is true with asynchronous logic, he said. His research shows
that it will be possible to double the switching speed of conventional
clock-based circuits, he said, and he is confident that Sun in particular
will soon begin to take advantage of that speed. "A 2X increase in speed
makes a big difference," he said, "particularly if this is the only way to get
that fast."
On the flip side, you probably missed Paul DeMone on P4 clocking from ISSCC, though you might have seen the original talk. realworldtech.com
The Pentium 4 also incorporates advanced features for custom deskewing each device during
testing. Each of the 47 domain clock buffers incorporate delay adjustment capabilities using a
programmable delay element controlled by a 5 bit register. The clock distribution system also
includes 46 phase comparator circuits placed between adjacent domain clocks that are
observable from a common test access port. This allows the 47 processor clock domains within
the processor to be deskewed during test using a binary search algorithm. When this process is
completed, the delay setting for each domain buffer is permanently programmed using fuse arrays.
The inter-domain clock skew of a raw Pentium 4 device may exceed 60 ps, but after domain
buffer deskewing that figure can be reduced to about 16 ps. The reduced level of clock skew can
increase maximum operating frequency by up to 10%. This programmable domain clock buffer
scheme also provides the capability of deliberately introducing controlled clock skew between
various regions of the processor core. By passing timing slack from pipeline stages that have short
logic delays to pipe stages with the longest logic delays, it is possible to further raise the maximum
operating frequency. Intel reported that tests with early silicon samples showed that devices could
be promoted by up to one full speed bin using this technique. |
