Hi all; All computer systems start out with bugs. Most finish that way. Here's some i840 highlights: (My favorite is #16, it gives you a warm fuzzy feeling about Intel chipsets.)
Intel 840 Chipset: 82840 Memory Controller Hub (MCH)
Specification Update, Intel, January 2001
2. Current Calibration
Problem: The 82840 MCH drives the RDRAM DQB signals following current calibration operation.
Implication: This may interfere with the current calibration activity that is occurring simultaneously. This issue only affects designs with memory repeater hubs, MRH-R.
Workaround: Current calibration should be disabled when using the MRH-R.
Status: There are currently no plans to fix this erratum.
5. NAP Exit
Workaround: Nonte identified. The NAP feature should not be used.
Status: There are currently no plans to fix this erratum.
15. False ECC Error
Problem: The MCH can incorrectly report an ECC single bit error in QW0 or QW2 when the MCH is running in ECC Mode or ECC Mode with hardware scrubbing. This incorrect reporting is isolated to the first ECC bit transported on the DQB8 signal in either QW0 or QW2.
Implication: False single bit errors can be reported by the MCH.
Workaround: This isolated ECC error can be filtered by BIOS.
Status: This erratum was fixed in the B2 stepping.
16. Lock Cycle Hang
Problem: The problem occurs when the processor issues two consecutive lock cycles directed toward the P64H (or ICH). During the first lock cycle, the MCH must have at least 6 memory read transactions posted by the P64H (or ICH) and an ICH DMA transaction in progress. This ICH DMA must be targeted toward main memory by the 8237 DMA controller in the ICH, an LPC SIO device, or ISA device.
Implication: The above conditions will lead to system lockup. The conditions required for this erratum to occur appear to be unlikely in actual PC systems. In many hours of testing on a number of actual PC systems, Intel did not observe this erratum. However, customers should be aware of this erratum and determine its potential applicability to their system configuration.
Workaround: None identified.
Status: There are currently no plans to fix this erratum.
17. MRH-R Stick Channel Swap
Problem: When the MCH Stck Channel Swap feature (Device 0, Function 0, Register 97h, Bit 6) is enabled the MCH can incorrectly swap stick channel operations during data transfers. This issue only occurs when the MCH Rambus interface is operating at 400 MHz.
Status: There are currently no plans to fix this erratum.
18. Missing Defer Reply Occurs under Certain Conditions
Problem: The 82840 MCH may stop responding to AGP FRAME# read cycles if the following conditions occur:
* Heavy AGP FRAME# traffic (reads and writes)
* Processor -to- AGP reads
* Heavy PCI, LPC, AC'97, traffic or processor Lock cycles
Workaround: There are two possible workarounds to this erratum:
* Disable Hub Interface A Combining, and AGP Write Streaming by writing a "1" to register F4h, bits 19 & 20.
* Disable AGP Read Snoop Ahead by writing a "1" to register F4h, bit 0.
Note: Workaround #2 could have a performance impact on AGP.
Status: This erratum was fixed in the B2 stepping.
21. NAP Failure
Problem: With NAP mode enabled the MCH may hang, causing an infinite number of random cycles to be issued to the memory interface.
Implication: NAP mode is not functional. System may hang if NAP mode is enabled.
Workaround: None identified. NAP mode, which is currently disabled in 82840 MCH B1 silicon, must remain disabled with B2 silicon.
Status: There are currently no plans to fix this erratum.
developer.intel.com;
-- Carl |
