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Technology Stocks : Rambus (RMBS) - Eagle or Penguin

RMBS 101.61

+2.8%

Dec 5 9:30 AM EST

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To: Bilow who wrote (67566)	3/13/2001 7:33:17 PM
From: Bilow	Read Replies (1) of 93625

Hi all; More seamy side of RDRAM (like any other) chipsets... The reason for posting these here is to make it clear that minor problems are common in early production chipsets. And do note that if it didn't leave the factory, Intel wouldn't be putting out an errata list on it. Intel® 82850 Memory Controller Hub (MCH) Specification Update 2. Direct RDRAM* NAP Mode Problem: With NAP mode enabled, the MCH may hang, causing an infinite number of random cycles to be issued to the memory interface. Implication: NAP mode is not functional. Workaround: None identified. The NAP feature should not be used. Status: Intel has no fix planned for this erratum. 3. Invalid Graphic Aperture Access Problem: Memory write access through the graphic aperture targeted above TOP memory or invalid memory location will cause the system to hang. Implication: If an invalid graphic aperture access is executed, the system will hang. Below are two scenarios that could cause an invalid graphic aperture translation: * Write to aperture entry is marked as "invalid" * Write to aperture entry is marked as "valid", but does not point to physical memory Workaround: None. Status: Intel has no fix planned for this erratum. 5. Sustained PCI Bandwidth Problem: During a memory read multiple operation, a PCI master will read more than one complete cache line from memory. In this situation, the MCH pre-fetches information from memory in order to provide optimal performance. However, the MCH cannot provide information to the PCI master fast enough. Therefore, the ICH2 terminates the read cycle early to free up the PCI bus for other PCI masters to claim. Implication: The early termination limits the maximum bandwidth to ~90MB/s. Workaround: None Status: Intel has no fix planned for this erratum. 6. RDRAM Interface Initiate Initialization Operation (IIO) Bit Problem: The Initiate Initialization Operation (IIO) bit in the RDRAM initialization control management (RICM) register may be cleared by the MCH too early. Implication: If the MCH clears the bit too early and BIOS immediately issues a new initialization op code (IOP), the MCH may incorrectly control the RDRAM CMD signal causing an invalid cycle to write to the memory subsystem, and the IIO bit may not be cleared. This results in a system hang during the memory initialization process. Workaround: BIOS must allow at least 1us delay between executing the initialization opcodes (IOP). Status: Intel has no fix planned for this erratum. developer.intel.com; -- Carl P.S. Re Mitsubishi. Don't make me laugh! Everybody knows that these royalties depend on the results of the trials.

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