Joe: One thing I am wondering about if the CPU stops while the change in frequency is occuring, or if it continues to operate, in other words, is the CPU stalled for 200 ms, or is the 200 ms the time it takes to go from one state to another, while the CPU continues to operate?
What PowerNow! 2.0 does is open to debate, but the current version of PowerNow! appears to stall:
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5.3 Dynamic Core Frequency and Core Voltage Control
PowerNow!-enabled processors support the ability to change
the bus frequency divisor and core voltage transparently to the
user during run-time. These features are implemented in
conjunction with a new clock control state—the EPM Stop
Grant state. For PowerNow! state transitions, the EPMR
register is accessed using a SMM handler. The SMM handler
initiates core voltage and frequency transitions by writing a
non-zero value to the Stop Grant Time-out Counter (SGTC).
This action automatically places the processor into the EPM
Stop Grant State and transitions the CPU core voltage and
frequency to the values specified in the Voltage ID Output
(VIDO) and Internal BF Divisor (IBF) fields of the BVC field.
Once the timer of the SGTC has expired, the EPM Stop Grant
State is exited and the PowerNow! state transition is
completed.
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(Source: p154 of the mobile K6-2+ Processor Datasheet)
EDIT: p286 explains further...
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13.2 Stop Grant State
Enter Stop Grant State
After recognizing the assertion of STPCLK#, the Mobile
AMD-K6-2+ processor flushes its instruction pipelines,
completes all pending and in-progress bus cycles, and
acknowledges the STPCLK# assertion by executing a Stop
Grant special bus cycle. After BRDY# is sampled asserted
during this cycle, and after EWBE# is also sampled asserted (if
not masked off), the processor enters the Stop Grant state. The
Stop Grant state is like the Halt state in that the processor
disables most of its internal clock distribution in the Stop Grant
state. In order to support the following operations, the internal
PLL still runs, and some internal resources are still clocked in
the Stop Grant state:
- Inquire cycles: The processor transitions to the Stop Grant
Inquire state during an inquire cycle. After returning to the
Stop Grant state following the inquire cycle, the processor
does not execute another Stop Grant special cycle.
- Time Stamp Counter (TSC): The TSC continues to count in
the Stop Grant state.
- Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
FLUSH# is not recognized in the Stop Grant state (unlike while
in the Halt state).
Upon entering the Stop Grant state, all signals driven by the
processor retain their state as they existed following the
completion of the Stop Grant special cycle.
Exit Stop Grant State
The Mobile AMD-K6-2+ processor remains in the Stop Grant
state until it samples STPCLK# negated or RESET asserted. If
STPCLK# is sampled negated, the processor returns to the
Normal state in less than 10 bus clock (CLK) periods. After the
transition to the Normal state, the processor resumes execution
at the instruction boundary on which STPCLK# was initially
recognized.
If STPCLK# is recognized as negated in the Stop Grant state
and subsequently sampled asserted prior to returning to the
Normal state, a minimum of one instruction is executed prior to
re-entering the Stop Grant state.
If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or
SMI# are sampled asserted in the Stop Grant state, the
processor latches the edge-sensitive signals (INIT, FLUSH#,
NMI, and SMI#), but otherwise does not exit the Stop Grant
state to service the interrupt. When the processor returns to the
Normal state due to sampling STPCLK# negated, any pending
interrupts are recognized after returning to the Normal state.
To ensure their recognition, all of the normal requirements for
these input signals apply within the Stop Grant state.
If RESET is sampled asserted in the Stop Grant state, the
processor immediately returns to the Normal state and the
reset process begins.
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-fyo |
