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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 237.62

-7.2%

Nov 6 3:59 PM EST

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To: Scumbria who wrote (33442)	3/25/2001 10:26:10 PM
From: fyodor_	Read Replies (1) of 275872

Scumbria: That's my point. The small single-ported cache is an unacceptable tradeoff to save one cycle of access. The extra cycle latency in Athlon can almost always be hidden in the pipeline, which makes the 2-cycle decision for P4 just plain stupid. I tend to think of the L1 cache in the P4 as more of a "buffer" than a cache in the traditional sense (although not being a processor designer, there's a good chance I've just butchered the terminology). The L2 then fulfills the role of a unified L1-data/L2 cache (which is actually 100% correct for floating point). With an impressive 6 cycle access latency, it does fairly well overall. Would you have condemned the architecture as much if Intel had "hidden" their L1 data cache as a buffer? There seems to be very little information available on the L1 instruction (trace) cache, so I don't really know what to think about it. -fyo

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