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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 255.96+2.3%3:59 PM EST

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To: Scumbria who wrote (33449)3/25/2001 11:15:33 PM
From: fyodor_Read Replies (1) of 275872
 
Scumbria: An L1 cache is absolutely essential for performance. Latency to the L2 is too long to hide in the pipeline, and the 8% miss rate in P4 is unacceptable (compared to 2% on Athlon.)

While the P4s L2 access latency isn't as good as the Athlon's L1, it's not too far off.

P4 L1: 2 cycles
Athlon L1: 3 cycles
P4 L2: 6 cycles
Athlon L2: 10+ cycles

Besides the high miss rate, the single-ported data cache chokes off the peak IPC to 1.0, which further strangles performance.

Again, I think of the L1 cache more as a buffer than a "real" L1 cache (which addresses my view of you hit-rate concern). Could you explain the IPC cap in more detail? TIA

Combine this with the excessively deep pipe, the small trace cache, and the large die size and you have a real POS processor.

The deep pipeline may be a problem in terms of absolute performance, but as McMannis would say: MHz sells.

How large is the trace cache anyway? 8kB? 16kB? more?

The die size we can agree on completely. We'll see what happens with the shrink, but I fully expect the die size of Northwood to be half that of Willamette - and that's including the extra 256kB L2 cache. If IPC can be further improved through activation of "dark transistor" broken features, that would only be a bonus.

So yes, the die size is completely unreasonable for Willamette. The shrink will do much to fix that (so much more than an optical shrink). Thoroughbred with 512kB L2 cache vs Northwood with 512kB L2 cache could be a much closer comparison in terms of die size.

-fyo
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