SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 246.76-0.5%Nov 14 9:30 AM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (33476)3/26/2001 9:55:31 AM
From: bacchus_iiRead Replies (1) of 275872
 
RE:"the small single ported P4 cache is inadequate to support one thread, much less multiple threads."

For me the big question is how the trace cache will be managed in multiple threads. Will they split the cache in as many sections as there are threads? Will they let the trace cache being polluted by others threads inserted instructions?

Frankly, in multiple threads mode, I don't understand anymore the usefulness of the trace cache at all.

Gottfried
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News