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To: Elmer who wrote (131380)3/30/2001 10:33:17 PM
From: muzosi  Read Replies (1) of 186894
 
Also an RTL model is never as good as a gate level model because of timing effects

It would indeed be a very broken design if your timing, especially at the boundary, changes after you do your synthesis and layout. Most of what's involved in those activities is "meeting timing". Also emulation is not for "timing" but for speed. Timing always changes between your fpga based emulation and the standard cell process.

Muzo
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