Intel Corporation (INTC) Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC)

INTC 38.16

+2.5%

Nov 7 9:30 AM EST

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: fp_scientist who wrote (133094)	4/22/2001 6:09:04 AM
From: fyodor_	Read Replies (1) of 186894

fp_scientist: My suspicion is that most of the advantage may be memory bandwidth but I don't know for sure. It will be interesting for me to find out how the P4 performs with DDR for my application when it becomes available. I have to agree with Elmer that you should try and get your hands on an Intel compiler. My own experiences with them aren't too hot, but if you can get some SSE2 usage in there, you might see a nice performance increase. Of course, it all depends ;-). Your code sounds like it might well be bandwidth limited, in which case you may not see much of an increase from SSE2. Supposedly, the use of SSE2 added only around 5% to the P4s SPECfp scores (but then SPECfp is _very_ bandwidth sensitive). Have you by any chance tried your stuff on a SDR Athlon? If so, how did that compare to the DDR Athlon? -fyo

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next