Taiwan's foundry titans duel for 0.13-micron supremacy
By Anthony Cataldo
EE Times
(04/27/01 12:47 p.m. EST)
SAN JOSE, Calif. — The world's two biggest semiconductor foundries — Taiwan Semiconductor Manufacturing Co. Ltd. and United Microelectronics Corp. — have opened their 0.13-micron process technologies and kicked off a high-stakes battle for technology supremacy in the face of one of the chip industry's worst slowdowns on record.
Although TSMC's and UMC's technologies appear evenly matched in several areas, the companies are taking different tacks with low-k dielectrics and on-chip memory, and these features could have profound implications for RC delay, chip size, performance and power consumption.
Both companies are scrambling to put the final touches on their process technologies. They're also beefing up marketing efforts and taking their shows on the road to woo fabless semiconductor companies and so-called integrated device manufacturers.
TSMC said two of its customers are already in volume production at 0.13-micron design rules, and seven more are being readied for production. The company said it plans to have 40 more 0.13-micron designs in production by the third quarter.
Both foundries see 0.13-micron as a milestone, and said their processes are equal to any now available. "We don't intend to be the top student in every class, but we do expect to get straight A's," said Shang-Yi Chiang, the company's vice president of research and development, at a technology forum here sponsored by TSMC.
There are several reasons why the foundries are crowing:
Their poly gate lengths at the 0.13-micron node are now below 100 nanometers, which helps bring gate delays down to 10 picoseconds. Gate densities, meanwhile, now exceed 200,000 gates/mm2.
They have successfully integrated low-k dielectric insulator materials between copper metal interconnect, bringing the effective RC delay for interconnect down by 20 percent or more.
Transistors with varying threshold voltages now come standard at 0.13 micron, opening up more device options and enabling the mixing of low-power and high-performance transistors on the same die.
But there are some glaring differences as well. UMC has opted to offer embedded DRAM as well as SRAM to give customers what it calls the widest range of density and performance choices.
Jim Ballingall, vice president of marketing for UMC, said the company is developing SRAM macros of up to 4 Mbits based on its six-transistor SRAM cell that measures 2.28 micron2. For customers that need 8 Mbits or more, the company is in the process of porting a 0.31 micron2 trench-cell DRAM that is six times smaller than 6T SRAM. UMC has been using a stacked capacitor DRAM in previous-generation process technologies.
The trench-capacitor DRAM cell was developed by IBM and Infineon Technologies, UMC's process development partners. Because the capacitor is buried in the substrate, it's ideally suited for integration with logic and won't degrade the performance of logic transistors, Ballingall said.
As an alternative to DRAM, TSMC will provide a one-transistor SRAM, which uses a planar capacitor but boasts SRAM-like speed. Smaller than SRAM built with a six-transistor cell but larger than a DRAM, the 1T SRAM will have a bit cell size of 1.1 micron2.
To be more competitive with DRAM in terms of density, the company is working with partner Mosys Inc. to introduce a 0.67-micron2 version of the 1T SRAM by early next year.
But TSMC is not writing off embedded DRAM. Rather, it is working on some new spins of a DRAM cell, including a metal-insulator-metal capacitor using a high-dielectric material.
Dielectric differences
TSMC and UMC are also divided on their choice of low-k dielectrics. Experts have pointed to the intermetal dielectric material as a critical area regarding wire delay, itself the largest contributor to total device delay. UMC's Ballingall said 80 percent of total delay comes from the interconnect.
Like its process partners, UMC has chosen to integrate the SiLK dielectric of Dow Chemical Co., which has a k-value of 2.65. That's a big leap from the fluorine-doped silicate glass (FSG) dielectrics in use today, which have a k-value of 3.6.
TSMC, however, considers SiLK to be risky. The highly porous material is mechanically weak and susceptible to thermal expansion, which can lead to problems during packaging, TSMC's Chiang said. SiLK also requires a barrier layer between metal that increases the material's effective k-value, he said.
TSMC's effective k-value using Applied Materials Inc.'s Black Diamond dielectric will be in the 2.9 to 3.0 range, said Chiang. The company estimates that will reduce RC delay 22 percent.
One side-effect of using low-k materials, however, is that metal and via electromigration gets worst compared to FSG. David Sheng, director of product marketing for TSMC, said the company is working to mitigate this effect, but said he doesn't think it will be a problem.
"It still meets our specs," he said. "I don't think our customers will really be concerned as long as we have a good margin compared to FSG." |
