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Technology Stocks : Intel Corporation (INTC)

INTC 35.53

-1.1%

3:59 PM EST

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To: Joseph Pareti who wrote (133636)	4/29/2001 3:36:50 PM
From: pgerassi	Read Replies (3) of 186894

Dear Joseph Pareti: Intel originally claimed that the L1 was 8KB because it was better to have 8KB at 2 cycle than 32KB at 3 cycle. This was supposed to increase the performance (read IPC). Is Intel accepting the fact that it screwed up and not used the larger more latency L1 cache as Scumbria first stated? And will it also include a data L1 cache? Will it include more decoders as the single x86 decoder isn't making it as far as IPC goes especially in multitasking servers and real time interrupt driven apps? The real reason for the 478 pin socket is to give the P4 more power to clock those transistors faster. The current socket does not have the power required to get P4 to 2GHz. Or will the number of the transistors increase to better balance the pipeline and thus, slow the clock increasing the IPC and overall performance? Just what Scumbria and others claimed. Oops, that means a redesign and another schedule slip. There goes this years profit for Intel. More creative accounting is needed to keep the stock price up. Pete

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