SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC)
INTC 35.53-1.1%Nov 14 9:30 AM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Tenchusatsu who wrote (133709)4/30/2001 12:49:37 PM
From: pgerassi  Read Replies (2) of 186894
 
Dear Tench:

Clawhammer will get a NB that uses HTT (LDT) to interconnect to SB, various other high speed busses like PCI-64 and PCIX, and to other NBs. N way is easy since a typical NB will have more than one HTT connection. 5 of them yields that diagram AMD showed a long time ago. A Sledgehammer with 5 HTTs and a single (or maybe dual) DDR or QDR DRAM memory bus allows for an N-way Flat (2D array) system (2 for each dimension plus 1 for chaining to PCI slots and SBs). 7 LDTs yields a Cubic (3D) system and 9 LDTs yields a Hypercube (4D) system. Only the number of chained links restricts the size in each dimension. 2 gets you 4 (8 cores) with Flat, 8 (16) with Cubic, and 16 (32) with Hypercube. 4 gets you 16 (32) Flat, 64 (128) with Cubic, 256 (512) with Hypercube.

As you can see, 8 way is easy with HTT.

Pete
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News