Hi cordob; Re the DDR data sheets... I'm wondering if you're completely familiar with the Direct Rambus bus design, in particular those parts having to do with RSL (Rambus Signalling Level).
Here's an RDRAM data sheet, but how RDRAM is used in a RIMM is not immediately obvious from the data sheet:
samsungelectronics.com
Here's a short form description (from memory, but I'm pretty good at these things, so this is generally correct):
The bus is relatively narrow, controlled impedance, and is terminated only at the end away from the controller. The controller end of the bus is left unterminated so that signals will double upon reflecting from it.
The termination resistors provide pull up on the bus. RDRAM and controller outputs are active low only.
Commands and data are sent down the bus as packets of length 8 (and width around 16 or 18), at an 800MHz data rate. Because of this number, actual transfers are always 16x8 = 128 bits. (DDR transfer are always 2-bits long multiplied by the width of the data bus. For a 64-bit wide bus, this means that every transfer is 128 bits long or longer.)
The design was originally specified for 3 RIMM sockets, but since mid 1999, this has been limited to 2 sockets.
Each RIMM may have up to 16 RDRAM chips, but I remember something about Samsung providing 32 chip RIMMs soon. The bus as a whole is limited to 32 chips by the packet logic (i.e. there is a 5-bit field that specifies which RDRAM chip is being addressed).
The controller sees the bus impedance, but the RDRAM chips, since they are on the middle of the bus, see half the bus impedance. But both driver types are designed for the same output drive strength. Controller outputs drive down the bus and are absorbed by the termination at the other end.
What's somewhat unusual is that RDRAM drives are half strength (in terms of voltage) because of the half impedance that the part sees in the middle of the bus. Two output signals propagate from the RDRAM, one half goes directly to the termination resistors and is absorbed. The other half is reflected at the controller end of the bus, and then travels back down the bus and is absorbed by the termination resistor.
Because of the above, each RDRAM must drive a signal onto a floating bus. For this reason, the output is constructed as a current source, instead of the more usual voltage source.
The current source RDRAM outputs have to be recalibrated continuously on the fly. This effect is similar to DRAM refresh but it uses bus time per RDRAM rather than using chip time for all the chips simultaneously. For this reason, the more chips added to the system, the more bandwidth is reduced by the current recalibration.
Because of the fact that RDRAM outputs have to drive into their own (or worse yet, other chips') reflected output signals, it is not possible to hook an oscilloscope up to the RDRAM output to see the "eye diagram". Instead, the eye diagram for RDRAM outputs is only valid at the controller pin. Eye diagrams for controller driven signals are valid at each RDRAM pin, of course.
Timing is provided by clocks that accompany the data bus and that are delayed by proportionately. (In this sense, RDRAM is similar to DDR in that it is "source synchronous" instead of "synchronous". Actually, if you read the DDR specs carefully, it is possible to read data out of DDR SDRAM chips synchronously, but when you send data to them, you have to send it along with a clock. I wouldn't call DDR SDRAM "synchronous", but I'm a bit of a purist.)
Two clocks are provided, one going towards the controller, the other going away. Naturally, data going towards the controller is synchronized with that clock and data going the other way uses the other clock.
Since upon powerup the chips high speed interface is uninitialized and therefore doesn't work, there is another bus to each RDRAM chip, with standard CMOS levels. That bus is used to initialize the parts. Initialization is amazingly complicated. (And you thought it was messy to initialize SDRAM...) Ah heck, I'll type in the list from the Samsung data sheet, and this is only the RDRAM initialization, the controller has another pile:
SIO Reset
Write TEST77 Register
Write TCYCLE Register
Write SDEVID Register
Write DEVID Register
Write PDNX, PDNXA Registers
Write NAPX Register
Write TPARM Register
Write TCDLY1 Register
Write TFRM Register
Give SETR and CLRR commands
Write CCA and CCB Registers
Powerdown Exit
Give SETF command
The controller is then brought up, and the output currents are measured and set.
One of the more interesting operations that must be performed is "RDRAM Read Domain Initialization". This is to figure out which read domain each RDRAM in each module occupies. "The programmed delay of each RDRAM is then adjusted so the total RDRAM read delay (propagation delay plus programmed delay) is constant." This is why adding RDRAM RIMMs to your system increases your latency.
-- Carl |
