Hi Gene Parrott; The last RDRAM is not on the end of the bus. The bus starts with a controller I/O pin on one end, and ends with a termination resistor at the other end. The RDRAM chips are all in the middle. As I stated before, the RDRAM chips all see Z/2, while the controller, being on one end of the bus, sees Z.
Re: "Because of the above, each RDRAM must drive a signal onto a floating bus." Floating isn't the right word, but I don't know what the right word is. Maybe a better way of putting what I am tring to say is that "Each RDRAM must drive a signal onto a bus that is not quiescent." By this I simply meant that the RDRAM outputs have to drive signals into a bus that does not start with any particular voltage. This simply implies that the RDRAM current sources must have a wide output compliance.
Re the data eyes... This is in reference to my note that the RDRAM outputs do not form data eyes except at the controller. You wrote: " Because the only place the "eye" is valid is at the controller pin, it makes no sense, (and is probably unintelligible), to look at an "eye" at the RDRAM output", and while what you wrote is true, it is also exactly what I wrote. What I implied, but did not spell out, is that it is traditional, when debugging systems, to look at signals both at the source and at the destination. With the RSL bus, this is impossible, at least for when RDRAM chips are driving. For this reason, it is a bus that is more difficult to debug.
Your other comments are more or less in agreement with me.
-- Carl |
