Carl, re:The total length of a fully populated 2-RIMM RSL bus, with two 16-RDRAM RIMMs installed is in excess of 4ns.
Regarding your timing analysis diagram, assume:
- Bus is populated as above.
- Distance between first and last chip on the bus is 2.5ns. Excludes bus length to controller and to terminations. (And an easy number to work with. <g>).
- Address and control propagate away from the controller toward the termination end.
- Read outputs propagate toward the controller end.
- Data rate 800MHz, (1.25ns cycles)
- Data width 1.25 ns.
If that's all there was to analyze you've got some real system problems. For example, assume consecutive reads of last chip, first chip. (N32, N1).
Using the above assumptions, looks to me like N32 will appear in reverse order long after N1. <g>
The solutions to this problem are probably very interesting and probably need to be known for a thorough analysis of RSL signaling.
At any rate, we know the solutions were found and that there can be consecutive data at 800mHz. As I mentioned in an earlier post, there is probably jitter, (I think controlled to <10%), but for purposes of my question let's assume there is none.
So what we have is consecutive 1.25ns wide data at 1.25ns cycles flowing on the bus and into the controller without overlap.
So the question is, if there is no overlap of data flowing on the bus, how can there be overlap at the data source on the bus?
TIA |
