Intel wrote about this feature in Intel Developer Journal, so I'm not sure why it is such a big surprise to Bert and everyone else.
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developer.intel.com
Managing the Impact of Increasing Microprocessor Power Consumption (continued)
Page 10 of 17
POWER REDUCTION MECHANISM
Once it has been determined that the die temperature is approaching the critical point, a mechanism is needed to quickly reduce power consumption, causing a drop in temperature. There are several key constraints in the design of this mechanism.
First, the latency between critical temperature detection and power reduction should be low. In this case, low latency refers to periods on the order of 100's of microseconds. Reaction times significantly longer than this would allow the die temperature to potentially reach a point at which it no longer operates reliably.
Second, the mechanism should be efficient. Here, efficiency refers to the ratio between power reduction and performance loss. An ideal mechanism results in a power vs. performance curve that is linear and crosses both axes at 0. In other words, if the power modulation mechanism results in a 10% performance loss while operating, it would also provide a 10% reduction in power consumption. Note an ideal relationship is only possible if frequency is the only variable.
Finally, the mechanism should add little or no cost to the design. Costs include those associated with die size, validation, platform impact, and risk.
After evaluation of a number of potential options, the Pentium® 4 processor design team chose a mechanism that utilizes the existing architectural low-power logic (the StopClock architecture). The chosen mechanism essentially provides an internal STOPCLOCK request to the processor core.
This STOPCLOCK request results in the clock signal to the bulk of the processor logic being stopped for a short time period. While this clock signal is stopped, the power consumption of the processor is reduced to a small fraction of the maximum processor power consumption. Because the STOPCLOCK request is a relatively high priority interrupt, the delay between the request and the resulting power decrease is relatively short, typically much less than 1 microsecond.
In order to minimize any potential impact to the platform, the time period during which the clock is stopped is kept small. The design target limits the total time during which the processor is not executing useful code to a few microseconds. This includes both the time the clock is actually stopped and the overhead associated with stopping and restarting the clock signal. |
