Ali,
Currently
Intel holds a patent that seems to be closest
to current Rambus implementation:
delphion.com
US6173345:Method and apparatus for levelizing transfer delays for a channel of devices such as memory devices in a memory subsystem
Hope it clears some confusions between patents and reality.
The following text is from the patent you refer to.
It makes it quite clear that the patent refers to a more efficient way of implementing the initialisation algorithm than that used hitherto. It refers to Rambus data sheets. The inventors do not claim to have invented the scheme used by Rambus, but to be enhancing it.
" A Rambus (TM) Direct Rambus Dynamic Random Access Memory (Direct RDRAM) bus is one example of a bus which utilizes memory devices along a channel. It is known that a Direct RDRAM Memory Controller (RMC) may expect to receive data from all devices along a channel during a particular bus cycle. In fact, a controller, described in "Direct RMC.d1 Data Sheet" available from Rambus Corporation of Mountain View, Calif., provides a controller delay register to assist in levelizing delays.
Additionally, one or more delay registers may also be provided within individual RDRAM devices (e.g., a TRDLY register discussed in the Rambus "Direct RDRAM 64/72-Mbit" Data Sheet at p. 36). Values may be stored in these registers in order to equalize delays between the various devices along the channel. Typically, the controller delay value is initialized first, then the delay values for individual memory devices are adjusted.
The prior art may not provide a mechanism to reduce the number of cycles performed during initialization. In general, the prior art may not specify particular ways to test only a subset of the total number of possible delay values. The prior art also may not specify a method of choosing initial values for certain delay testing iterations, an efficient order for testing delay values, a method for performing each test, or a way of aborting delay testing and disabling devices when certain values are reached. Thus, the prior art may not provide an adequate method for levelizing delays along a channel of devices. "
John |
