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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 249.66+7.6%3:59 PM EST
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To: minnow68 who wrote (45801)6/29/2001 11:12:17 PM
From: dale_laroyRead Replies (1) of 275872
 
>I would not be surprised at all in 2010 to see the average processor have 16 Megabytes of on-chip cache organized in as many as half a dozen levels.<

There should be at least a factor of eight increase in cache size between levels. Thus, assuming 16MB in L4, there should be no more than 2MB in L3, 512KB in L2 and 64KB in L1. Of course, this assumes essentially the same architecture for each cache level. Radical differences, such as Harvard Architecture for L1, or going from two-way set associative to sixteen-way set associative could justify much less than eight times the amount of cache in L2 as in L1. Even so, it would be difficult to justify more than five levels with only 16MB of on-die cache at the lowest level.
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