Paul, I do not believe. In contrast to you, I just know.
And concerning your speculations about memory, everything you have said is WRONG. I already told you this, but you did not learn. In modern chipsets, most memory accesses happen in burst mode, when the cache controller is trying to maintain the cache coherency. It is called a "cacheline fill". With proper read/write buffering in the chipset, these fills can be combined into longer bursts. For EDO DRAM this leads to much better "effective access time", if you prefer. SDRAM has some specifics that limits it from 2.5-fold increase in performance (please notice, 2.5X, not 5X). Details, as I said before,
could be found on Micron Web page, for example.
Yes, 100 is 33% faster than 66.6667. But overal effect of scenarios you mention is very small. You must know that the power of computing is realized through the numerous repetitive loops, otherwise the time for coding would never be justified. Sorry if this is off topic. - Ali |
