Paul - Re: "100MHz bus, AMD/VIA Technologies, and the valuable education I can provide them"
There is no need in that. They prfectly know what they are doing,
but I am not sure about you. You should learn better the technology
used by a company you invested in.
You failed to link two simple thoughts. I communicated to you the fact, so you can verify it. Why it happens? I can explain the two thoughts in simplified terms:
1. Because of transactions on the DIB are deferred, most of
cache fills can occur LATER while the PPro/P2 can do other
job via the independent L2 bus. Since the memory transaction
can be completed later, IT DOES NOT MATTER HOW LATER, and that
is why the performance is independent of the Slot 1 clock speed.
2. The Socket7 is much simpler - no deferred transactions, and CPU must wait for cacheline operations to complete since it cannot access L2 at the same time. That is why the overall performance is so bus speed sensitive. Faster bus - less wasted time - higher overall performance.
CONCLUSIONS (for local CS experts):
1. Slot-1 bus architecture already took most of advantages from
the sophisticated bus handling and has no significant benefits
from increased bus speed.
2. Socket-7 bus will benefit from the speed increase almost proportionally.
Now, a simple brain teaser for you, Paul: If today the K6
performance is on-par with P2 (clock-to-clock), which system
would have higher performance at 100MHz bus speed?
When you solve the problem, I grant you a permission to
communicate the result directly to Jerry, with all your
credits. BTW, if you need more explanations, do not
hesitate to ask.
Ali |
