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Technology Stocks : Intel Corporation (INTC)
INTC 48.60+3.5%Jan 20 3:59 PM EST
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To: Paul Engel who wrote (24910)6/18/1997 2:22:00 AM
From: Ali Chen   of 186894
 
Paul, you may speculate without grounds as long as you wish.
Even kids learn these days the difference between FACTS and
OPINIONS. I just was trying to do you a favor and explain the
fact of very complex behaviour in simplified terms. I do not
want to discuss the subject in wide philosophical terms like
"REAL SLOW" on "not real slow". I prefer "reasonable range of
parameters". And within this range of parameters my conclusions
(based on observations) have a very high likehood.

<Did you ever wonder how L1 and L2 caches get filled?>
You are telling me?

If you want the fallacy, it is here:
<However, for large numbers of write-back cycles,>
During regular operations, a x86 CPU CANNOT GENERATE
LARGE NUMBER OF BACK-to-BACK cycles. That is exactly the
general problem of x86 architecture, where it gets
saturated. Of course, other transfers (bus masters)
would benefit from the faster memory, but
THIS IS ANOTHER TOPIC.

Good night.
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