Integrated Memory Controller for Hammer Confirmed
viahardware.com
Ah, finally we have official word about this rumor:
Heyes revealed in his speech that the upcoming x86-64 line of Hammer (K8) processors would integrate their own memory controller, and use HyperTransport to communicate with an AGP8X and/or PCI-X tunnel, as well as a southbridge. This allows each processor in a SMP system to have its own, dedicated bus to memory, as well as a high-speed bus to AGP and PCI peripherals. This strategy may cut AMD's traditional partners, namely the third party chipset manufacturers, out of a substantial part of their core market. However, VIA is already working on their own Hammer chipset, which uses the K8T333 AGP8X "northbridge" sans memory controller, and the 237 HyperTransport southbridge.
And there's PC2700 support for Athlon coming:
VIA also pledged support for the upcoming DDR333 standard from Jedec. Taking DDR266 and upping the clock speed to 166MHz, DDR333 is fairly evolutionary compared to the jump to DDR from PC133. VIA plans to begin shipping DDR333 chipsets in the first half of 2002, with KT333, Pro333, P4X333 and P4N333. Due to VIA's pseudo synchronous design philosophy, running the memory bus at 33MHz faster then the system bus is completely possible, and doesn't incur the latency penalty a fully asynchronous design does.
Andreas |
