Dan, <Execpt when they're addressing video card memory, disk controllers, network cards, and other such devices that typically run under heavy load on a server.>
You don't understand, as usual. Processor-to-I/O traffic makes up a very small percentage of overall chipset traffic. I/O devices typically access memory directly instead of relying on processors to provide them data. That's why in server chipsets, the memory channel typically supports more bandwidth than even the FSB.
In the case of 760MP, AMD should have added a second DDR channel to balance out the bandwidth of the two EV6 interfaces. But I remember them saying that cost was a huge consideration in the 760MP design, which is why they stuck with one DDR channel. Guess you can't blame them, considering that the 760MP north bridge already has over 900 pins.
<PIII can address 8 locations with the same LSB (Least Significant Bits), P4 can address 12 (4-way instructions + 8-way unified L1/L2). Athlon can address 2 with its L1 + 16 more with its exclusive L2.>
And this is supposed to be a huge advantage, except on paper? Going from 8-way to 16-way isn't going to reduce cache thrashing that much. Not only that, but the latency of a higher-way cache is necessarily going to be higher.
But hey, what do I know? All I do is server chipsets for a living. ;-) I can't argue with the superb results that AnandTech showed, but I can argue with AMDroids who are emboldened by those results and act like armchair experts on this subject.
Tenchusatsu |
