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Technology Stocks : Intel Corporation (INTC)

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3:19 PM EST

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To: Dan3 who wrote (140417)	7/30/2001 3:52:45 AM
From: Tenchusatsu	Read Replies (2) of 186894

Dan, <Pretty much the whole point. On Athlon's point to point chipset, while the CPU is bursting bytes out to a NIC buffer, a DMA transfer can take place from the disk controller to RAM. On P4's bus chipset, it has to wait.> I don't get it, Dan. Why do you continue to act like an expert when every point you make is grossly inaccurate? If the CPU is bursting data to a network controller, that means the PCI bus is being occupied by the NIC. The DMA transfer from disk controller to memory has to wait until the PCI bus is freed. <On a big server with many processes, it will reduce it more than going from 256K cache to 2 meg cache, depending ont he software running.> Based on your previous inaccurate comments, I can safely assume that you have no idea what you are talking about in this case as well. Or do you think the developers of RISC processors like Alpha, UltraSPARC, and PA-RISC make grave mistakes when they pursue larger caches over increased set associativity? Give it up, Dan. You're beginning to look like Peter McNealy: winternet.com Tenchusatsu

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