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To: pgerassi who wrote (140432)7/30/2001 1:17:02 PM
From: Tenchusatsu  Read Replies (1) of 186894
 
Pete, amazingly enough, I can't find anything in your recent post to disagree with. Except this:

<Another curious fact is that 4 ways composed of two pairs of Xeons on two separate busses are much faster than four Xeons on a single bus. It shows both in database loads and web serving loads. This shows that the bus concept does not work well going from 2 to 4.>

That statement is a little unfair. There's no way that a 700 MHz hefty-duty processor ISN'T going to be limited by a 100 MHz bus. (C'mon, a 7:1 processor-to-bus clock ratio?) Even huge caches can't serve as a total workaround. But hey, going from 2-way to 4-way on that 100 MHz bus still results in a substantial performance benefit. It might not be 100% linear, but it's good enough for now.

<It appears that AMD and DEC were justified in their belief that P2P links were better than busses to connect CPUs to chipsets.>

Obviously P2P links are better. They are also more expensive and harder to implement as well. We already saw this: AMD took their sweet little time getting to 2-way SMP, and they finally accomplished it with an expensive 900-pin north bridge. (Of course, the high cost is partially offset by AMD's willingness to sacrifice profits.)

Tenchusatsu
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