" Channel lengths are not part of the copper process steps."
You are correct that the interconnects are not part of the copper process steps. But, and this is assuming that I understand it properly, you have to control the interconnects pretty tightly to get really small Leffs. To insure that there is enough Al to fill the channel, the tolerances need to be much wider than with Cu.
Of course, I could be totally wrong here...
I will have to review what Paul said again. If he was referring to physical channel length, then we were discussing different things here, that is what I get for going from memory. I do agree that AMD has pushed their process beyond what is typical for a 0.18 micron process, I believe this is the reason why they did that sudden change in direction in early 2000, their current process didn't yield much for them when they tried the shrink to 0.13 micron. So they had to re-work their approach. Since they haven't released any information that I know of about their bulk SI process, the only information they have let out is about their SOI one, I don't have a clue what they will be doing different. In particular, I can't say what their projected physical channel lengths are for their bulk SI. Hmm, come to think of it, the announcement about using the Black Diamond dielectric might be for their bulk process. If it is for their SOI process, then it would be the only thing different that I can find from IBM's SOI process, with the possible exception of the thickness of the oxide layer. IBM uses SiLK for their low-k dielectric... |
