so, what's the catch?
I'm not sure. For one thing, they don't compare their NROM to 2-bit/cell or the planned 4-bit/cell versions of Flash. The respective effective cell sizes for each would be:
single-bit Flash ~8F^2
double-bit Flash ~4F^2
quad-bit Flash ~2F^2
NROM ~2.5F^2
OUM ~4.5F^2
Last I heard, Intel's 4-bit Flash was supposed to debut around the beginning of 2003 -- presumably they're still working on it? The multi-bit Flash versions also have to be handicapped somewhat since they are more expensive to make than the single bit versions (I'm not sure exactly why). The plastic technology is also a candidate for solid-state storage supremacy with its 8X+ cost advantage potential, but most likely much more in the speculative/time_frame_uncertain category.
Another question I have is their mask-steps count:
They claim 4 extra mask steps beyond what is required for CMOS to create the NROM array with "high voltage transistors" -- 2 extra mask steps without the transistors. They compare this to Flash, which they say needs 10-12 mask steps beyond the CMOS. I thought Tyler had said that CMOS is about 20 masks, and I have heard about the same number for Flash, i.e., there is not this claimed 10 mask differential between CMOS and Flash. Plus, I believe that SSTI claims their SuperFlash is done with ~14 mask steps. So, their great cost savings in process steps is a questionable claim to me, although I'm not nearly familiar enough with the area to be sure. As a side note to this -- what are these "high voltage transistors" they are talking about?
Their performance looks about equal to that of Flash, although, again, I'm not totally sure of my data-sheet interpretations.
The biz-tech article quoted 100uA/bit write access -- which is about 1/10 of what I think Flash uses. They also say 2 Mbytes/sec data rate, which is about equal to Flash. Since I think access current is the limiting factor for the amount of parallelism in an access (the inter-chip bus is power-constrained), I would deduce that their per-bit access times are about 10X longer than that for Flash, which would even them up in net data rate. This deduction squares well with the write times illustrated in this paper:
saifun.com
which is linked from this website:
saifun.com
Here's a table of data comparing the performance characteristics of DRAM, Flash, OUM and NROM (work in progress).
frontiernet.net
Here's the links to the DRAM and Flash data-sheets I used:
toshiba.com
amd.com (the AMD site is having a problem tonight)
The NROM folks also claim easy embeddability on logic chips, which of course is a huge advantage.
It's hard to say if NROM will change the competitive landscape for OUM from what it would have been without NROM -- there's probably some applications that would be a good fit for its cost/performance equation that would otherwise have gone to OUM.
My comparison table shows how OUM is an order of magnitude above Flash in data rate and an order of magnitude below DRAM. It also shows how totally superior it is in write energy. These are the reasons why Intel calls it a next-gen memory rather than a storage technology like Flash, NROM, or the polymer FeRAM. Intel likes OUM because it's good enough for memory and cheap enough for storage, so that there is the extra benefit of needing only one type of memory in most portable applications, which saves a lot in cost. And if higher performance is needed, the anticipated CMOS-compatibility allows for easy addition of DRAM or SRAM.
The write-energy for DRAM in my table is not realistic since it doesn't include the set-up operations and the refresh cycles. I'm assuming 64-bits per access for OUM, since that makes it equal in current consumption (approximately) to Flash. I think power is the critical quantity here, but that's dependent on voltage, and Flash is being made at 1.8v now, so the current (mA) comparison is good enough.
I don't know why DRAM is able to have 80mA per access as compared to 10mA for Flash. |
