LSI Logic prepares 0.10-micron process, balanced foundry path for new growth
Foundries will 'crank up' to 30% of company's products in next several years, says Corrigan
By Mark LaPedus
Semiconductor Business News
(08/27/01 11:43 a.m. EST)
MILPITAS, Calif. -- Providing a glimpse into the company's chip-manufacturing strategy, LSI Logic Corp. officials here told SBN that the chip maker will soon deliver its first 0.13-micron ICs with copper-interconnects and other advanced features.
The application-specific IC giant has also quietly developed its first test chips, based on a next-generation 0.10-micron process technology, according to high-level executives. This technology, which includes copper-metal interconnects and low-k dielectrics. The 0.10-micron process is scheduled to move into volume production in 2004--or sooner, said executives in a briefing for .
Moving forward, LSI Logic is mapping out a technology course to fight competitors on two separate market fronts: ASICs, which are morphing into system-on-chip designs, and ever-present threat of higher-density programmable logic devices.
"You will always have an ebb and flow between ASICs and standard products [in the market]," said Wilfred Corrigan, chairman and chief executive officer of LSI Logic. "But if you look at where the market is going, you have to go with ASICs, because of cost," said Corrigan in an interview at the company's headquarters.
In the traditional ASIC markets, LSI Logic is going head-to-head with a range of rivals, including Agere, IBM Microelectronics, NEC, Toshiba, and others with system-on-chip know-how. But LSI Logic also plans to keep the field-programmable gate array (FPGA) suppliers at bay, including the likes of Altera Corp. and Xilinx Inc. LSI Logic is working on aggressive new strategies to compete with high-density FPGAs that have moved out of development and low-volume applications with a range of standard functions for mainstream applications.
Part of the new strategy is to leverage more outside foundry capacity. LSI Logic has taken a major step in that direction under a joint-development pact with Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), which is providing the basis of its own 0.13-micron technology for new products. The development and foundry alliance will allow LSI Logic to transfer the TSMC 0.13-micron process to its own wafer fabs (see April 4 story).
LSI Logic officials declined to say whether or not the company is collaborating with TSMC on the follow-on 0.10-micron process technology, but analysts have speculated that the two companies are jointly developing this process as well.
Currently, Milpitas-based LSI Logic makes the majority of its chips in its own wafer fabs. Only 6-8% of the company's integrated circuits are produced in various silicon foundries.
While LSI Logic will continue to fabricate its own ICs, the company plans to increase its production at the foundries by five-fold going into the future (see April 5 story).
"We will use both [our own fabs and foundries]," Corrigan said. "We also have relationships with several foundries. We will crank up our production at the foundries to 30% over the next several years," predicted the CEO.
But the LSI Logic executive dismissed industry speculation that the company is headed towards a fabless model. It is widely assumed that mid-sized chip companies, like LSI Logic, are on the "bubble" to move ahead and build new fabs, especially the costly 300-mm wafer plants.
It's doubtful that LSI Logic will build any 300-mm plants, thereby forcing the company to embrace the foundry model, noted analyst Carl Johnson, president of Infrastructure, a market research firm. "I don't think you will see LSI Logic build a 300-mm fab."
LSI Logic is still evaluating its 300-mm fab plans, according to Corrigan. "Everybody is looking at 300-mm," he added, referring to the industry's dilemma of using larger diameter substrates to drive down the cost of chips.
But LSI Logic is also taking actions to cut its near-term costs in the current downturn, consolidating manufacturing. In April, the company announced the closing of its fab in Colorado Springs, Colo., and it took a $120-to-$150 million charge along with reducing its workforce by 500 employees, or 7% or its jobs (see April 11 story).
"The mature technologies utilized by the Colorado Springs facility have been particularly impacted by the decline in the overall economy," Corrigan said back in April. "We are consolidating our manufacturing capacity at our two major sites in Gresham, Ore., andTsukuba, Japan."
In addition to the Gresham and Tsukuba wafer fab plants, LSI Logic operates an 8-inch facility in Milpitas for R&D. That wafer processing frontend is currently capable of processing devices with 0.11-micron feature sizes.
The company's main, high-volume production fab in Gresham uses 8-inch (200-mm) substrates to fabricate 0.35-to-0.13-micron ICs. The company's fab in Japan is an older 6-inch (150-mm) wafer-processing plant, using 0.35-micron technology.
To handle next-generation ICs, look for LSI Logic to be turning more of its volume production over to outside foundries. In the last 1990s, the ASIC pioneer began dabbling with pure-play foundry providers by striking an alliance with Singapore's Chartered Semiconductor Manufacturing Pte. Ltd.
While Chartered is still one of LSI Logic's partners, the Milpitas-based company has been branching out its use of foundries. Two years ago, LSI Logic surprised many industry observers by announcing a pact with silicon foundry startup Silterra Malaysia Sdn. Bhd. The startup in Kulim, Malaysia, gained access to LSI Logic's 0.25-micron G1+ technology as well as its 0.18-micron G12 process under the alliance (see May 19, 1999, story). LSI Logic also has a small stake in the Malaysian startup.
"That's going very well," said Corrigan, referring to LSI Logic's work with Silterra, which is now ready to ramping a new 0.18-micron process into production after starting up its initial 0.25-micron wafers at the start of this year (see Aug. 8 story).
But to significantly increase its use of foundry volumes, LSI Logic entered into its major pact with Taiwan's TSMC for copper and low-k dielectric ICs. The joint-development efforts will combine LSI Logic's transistor modules with TSMC's 0.13-micron copper and low-k dielectric technology. The partners expect to move the 0.13-micron process to LSI Logic's fab lines by late 2002 or early 2003. LSI Logic refers to its 0.13-micron process as Gflx.
The LSI Logic/TSMC alliance is still on track, Corrigan said, who expects his company to be delivering 0.13-micron products fabricated by TSMC "towards the end of the year."
Volume production of the jointly-developed, 0.13-micron process is slated for the first half of 2002, said Ronnie Vasishta, vice president of technology marketing. "There's a lot of interest in 0.13-micron technology," Vasishta said in an interview last week.
Right now, LSI Logic is shipping products based on other designs rules. "A lot of what is in production is G11, which is our 0.25-micron technology," he said. "Most of what is in design is G12, which is 0.18-micron."
But surprisingly, the company is far along on its 100-nm (0.10-micron) program. It has developed its first transistors and test chips based on the technology, which includes copper-interconnects, low-k dielectrics, and other advanced features, he said.
"We've developed our first silicon at 100-nm," Vasishta told SBN. "I would say that we will have our first [100-nm] libraries in the middle of 2003. Production will be in 2004." The 0.10-micron copper process will use a dielectric insulator with a k rating of 2.9. (The TSMC-base 0.13-micron process uses fluorinated silicate glass, or FSG.) LSI Logic declined to comment if the company is developing its 100-nm process with TSMC. |
