YES! Big, big patent news!!!
patft.uspto.gov;
United States Patent 6,282,145
Tran , et al. August 28, 2001
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Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
Abstract
Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.
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Inventors: Tran; Hieu Van (San Jose, CA); Khan; Sakhawat M. (Sunnyvale, CA); Korsh; George J. (Redwood City, CA)
Assignee: Silicon Storage Technology, Inc. (Sunnyvale, CA)
Appl. No.: 231928
Filed: January 14, 1999
Current U.S. Class: 365/230.06; 365/51; 365/63
Intern'l Class: G11C 008/00; G11C 005/02
Field of Search: 365/63,230.06,51
SUMMARY OF THE INVENTION
This invention describes the design method and apparatus for a super high density nonvolatile memory system capable of giga bits as applied to the array architecture, reference system, and decoding schemes to realize the optimum possible number of storage levels within specified performance constraints. Method and apparatus for multilevel program and sensing algorithm and system applied to flash memory is also described in this invention. Details of the invention and alternative embodiments will be made apparent by the following descriptions.
The invention provides array architectures and operating methods suitable for a super high density, in the giga bits, for multilevel nonvolatile "green" memory integrated circuit system. "Green" refers to a system working in an efficient and low power consumption manner. The invention solves the issues associated with super high density multilevel memory system, such as, precision voltage control in the array, severe capacitive loading from MOS transistor gates and parasitics, high leakage current due to memory cells and from cells to cells, excessive power consumption due to large number of gates and parasitics, and excessive memory cell disturbs due to large memory density.
An aspect of the invention provides an Inhibit and Select Segmentation Scheme that makes use of a truly-floating-bitline scheme to greatly reduce the capacitance from junctions and parasitic interconnects to a small value.
The invention also provides a Multilevel Memory Decoding scheme which is capable of greater than 10-bit multilevel operation. The Multilevel Memory Decoding Scheme includes the Power Supply Decoded Decoding Scheme, the Feedthrough-to-Memory Decoding Scheme, and the Feedthrough-to-Driver Decoding Scheme. The Multilevel Memory Decoding scheme also includes a "winner-take-all" Kelvin Decoding Scheme, which provides precise bias levels for the memory at a minimum cost. The invention also provides a constant-total-current-program scheme. The invention also provides fast-slow and 2-step ramp rate control programming. The invention also presents reference system method and apparatus, which includes the Positional Linear Reference System, Positional Geometric Reference System, and the Geometric Compensation Reference System. The invention also describes apparatus and method of multilevel programming, reading, and margining.
Method and apparatus described herein are applicable to digital multilevel as well as analog multilevel system.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.
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This is the one I've been waiting for!! Read it right.. THIS is the Agate high density stuff I've been waiting for!! Read it right.. 10-bit-per-cell flash!! Gigabit flash..
all the best, docpaul |
