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Technology Stocks : Intel Corporation (INTC)

INTC 37.83

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Dec 12 3:59 PM EST

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To: Saturn V who wrote (142316)	8/28/2001 5:53:41 PM
From: Tenchusatsu	Read Replies (3) of 186894

Saturn, <Are you in a position to comment about the implementation of Jackson> Not really. All I know is that it doesn't take that much more silicon to add another thread to the pipeline. Of course, the real trouble is debugging the processor design. Two simultaneously running threads can potentially increase the validation space by an exponential factor. <It reminds me of IBM's dual processor on a chip, which was announced two years ago. This is two separate and complete CPU on a chip, but with a common L2. AMD's paper Sledgehammer sound very similar to the IBM approach.> One remarkable thing about SMT and CMP (chip-level multiprocessing, i.e. IBM's dual-core chip) is that they are not mutually exclusive. One could conceivably design a dual-core processor where each core runs two threads for a total of four simultaneous threads on one processor! Of course, the poor L2/L3 cache gets thrashed harder than a ... er, nevermind. Tenchusatsu

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