SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 242.19-1.7%Feb 3 3:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: pgerassi who wrote (53021)8/29/2001 2:50:41 PM
From: Saturn VRead Replies (3) of 275872
 
Pete Ref < L1 Data Cache and cache ways >

You probably spent at least one hour composing the terribly long message and analysis.

I almost got a headache trying to decipher your long winded post and the flawed analysis, and I am sure that several others must have had a similar experience.

However your analysis was way off on its basic assumption.

The P4 does indeed HAVE a L1 DATA CACHE.

Please read page 1-1 of the P4 manual
ftp://download.intel.com/design/Pentium4/manuals/24896602.pdf

It states that "P4 includes

On chip caches:
-8K high speed first level data cache
-12K micro op Execution Trace Cache
-256K Byte unified 8way second level cache"

So your entire analysis is fatally flawed. A quick check of the first page of Intel's manual, would have saved an hour of your time, and not wasted bandwidth.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext