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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 214.99

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Dec 26 9:30 AM EST

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To: Dan3 who wrote (53141)	8/30/2001 1:10:05 AM
From: wanna_bmw	Read Replies (3) of 275872

Dan, Re: "A medium sized 16-way cache is arguably higher performing (and more difficult to manufacture) than is a much larger 8-way." Dan, let me ask you a question that gets to the root of the problem. Which do you think would be more beneficial to database serving: a 4-way 4MB cache or a 16-way 256KB cache? You seem to be suggesting the latter, and I was hoping you would clarify. Also, let me remind you that adding more associativity does not make the cache more difficult to design. It only requires changes in logic that are straight forward to accomplish. Ask any designer on this forum. It becomes difficult to reduce access times, while at the same time increasing associativity, but that is another matter entirely. What is more difficult is designing a larger cache, because the larger number of transistors can cause a higher defect rate per die, and thus lower yields considerably. Therefore, the designer must include extra redundancy, which increases the size of the die. wanna_bmw

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