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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 203.14

-0.8%

Jan 9 3:59 PM EST

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To: combjelly who wrote (53577)	9/1/2001 7:34:09 PM
From: Tenchusatsu	Read Replies (2) of 275872

Combjelly, <You mean that the P4 doesn't slow to half speed when the decode unit is used?> Remember when the Athlon's L2 cache was off-chip and running at 1/2 to 1/3 the speed of the processor core? Do you think the Athlon slowed down to 1/2 or 1/3 speed every time it accessed the L2 cache? How about on an L2 cache miss? Do you think modern processors slow down to the speed of the FSB when going to the chipset's north bridge? There is little difference in performance between a trace cache that provides x instructions per clock and one that provides 2x instructions every other clock. Of course, I doubt that's going to change the minds of 'Droids who think Intel's processor architects can't grasp basic concepts like Flynn's bottleneck. Tenchusatsu

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