" There is little difference in performance between a trace cache that provides x instructions per clock and one that provides 2x instructions every other clock."
Never said that there was a difference. I do remember something in a whitepaper by Intel that such was the case, but I cannot find it right now. It could be that I don't remember it correctly. That can, and does, happen.
In addition, I have always had the greatest respect for Intel's engineers. I am, however, dubious about Intel's management. It may be a case of projection, I have worked for companies whose management made strategic decisions that wound up boxing in engineering, and that appears (to me at least) to be the case at Intel, and it appears to be what drove the P4. In my opinion, the management at Intel decided that PCs were commodities, performance was un-important and that high integration was the ticket. Since they were the market leader, they would be able to dictate the future and drive all of the technology, so Rambus memory and Timna was the chosen direction for the desktop. They were so confident about that, they didn't have any alternatives in the pipe, except for a few cancelled projects like the P4. When it became clear that they had made a mistake, there was a general scrambling around to try to come up with an alternative, and that brings us up to date. |
