Breaking Barriers in IC Interconnect Length, Layers
New technologies are appearing which finally offer ways to achieve higher-speed operation and to reduce interconnect line lengths and the number of layers. Existing technologies such as Cu interconnect and low-k materials have reached a barrier in these respects. New developments in this field were announced as part of the Focus Center Research Program (FCRP) national project, launched in the US in 1998, and include technologies to reduce interconnect line length with ultra-high density leads (12,000 leads/cm2), and multiple chip interconnects using three-dimensional (3D) wiring.
3-4GHz Limit
Faster integrated circuit (IC) interconnects are the single most important factor in improving system performance. Shrinking design rules boosts transistor operating speeds, but the circuit paths themselves dominate overall system performance.
Existing pattern technology spans two sectors: IC process and design. In regard to the IC process, the key development targets are low-resistance copper interconnect, low-k interlayer dielectrics, and process technology to integrate them. In the IC design sector, however, development focuses on optimizing the number of repeaters and wiring lengths in many branches, and boosting layout density.
Even with technologies from both sectors, however, the limit to the operating frequency seems to be "3 to 4GHz", according to Professor Takamaro Kikkawa of the Research Center for Nanodevices and Systems at Hiroshima University. The International Technology Roadmap for Semiconductors (ITRS), in fact, shows the chip clock frequency as 1.6GHz for 2001, but only 3.8GHz (2.4 times higher) in 2014, which represents four generations in design rule.
Shortening Interconnect
Many interconnect engineers feel that the biggest obstacle to boosting chip operating frequency is the massive affect of inductance (L) from the IC patterns. This L component has little affect at low frequencies, but as the frequency rises it causes noise and cross-talk problems.
Engineers are investigating a variety of measures to minimize or avoid the affects of the L component. These can basically be divided into two measures.
The first involves shortening the length of the IC interconnect, thereby reducing the affect of the L component. Technologies to reduce the length of wires between chips and packages include wafer-level chip scale packaging (CSP), while inter-chip wires can be reduced through, for example, 3D stacked chip layer wiring technologies.
The second measure involves inserting decoupling capacitors into the interconnects. Technology to build large-capacitance capacitors, now found on the mother board or package substrate, directly into the IC is a key development target.
While technologies for on-chip decoupling capacitors are still in the early stage, reduction technologies for IC interconnect length were presented at the 2001 International Interconnect Technology Conference (2001 IITC), held in the US in June.
Two technology announcements by the Georgia Institute of Technology, which plays a key role in the FCRP national project, were especially important. These include a technology for reducing IC interconnects with ultra-dense lead pads at 12,000 pads/cm2, and a technology that increases the IC interconnect design margin with 3D stacked chip wiring.
12,000 Leads/cm2
Most ICs have electrode pads in peripheral arrays, aligned along the edges of the IC, but the Georgia Institute of Technology predicts that an array of electrodes covering the entire surface of the chip will be needed for high-speed designs.
Their reasoning is as follows. First, interconnect lengths from the electrode pad to the circuit are shortened, making it easier to suppress the voltage drop on power supply leads. ICs designed for higher speeds generally have larger supply currents, which means a larger voltage drop to interconnect resistance. When supply interconnects are made wider to lower resistance, layout efficiency is reduced. Electrode array pads on the chip surface are advantageous here. In addition, the shorter length reduces noise on the supply lines due to gate switching.
Even with a planar array of pads, though, low-density connection pads won't be able to handle the demands of high-frequency signals above several gigahertz. Even if power supply noise can be suppressed, high-frequency current fluctuation in the circuits will generate noise in the return path, leading to instability in ground potential.
To prevent this from happening, the Institute minimizes the return path length by maximizing pad density (Fig 1). Called a "Sea of Lead" (SoL), the new technology uses wafer-level CSP to achieve a high density of 12,000 pads/cm2. With SoL, an air gap is formed between the electrode and the silicon substrate, helping alleviate stress in the vertical direction (Fig 1d). The group developed a process capable of handling the whole thing at the wafer level for lower cost. Georgia Institute of Technology Regents Professor Paul Kohl said that in addition to power supply applications, "the new technology can be used for clock signal supply and test burn-in leads as well."
Wider Design Margin, 3D
The 3D chip interconnect technology is generally used to expand memory capacity, but the Georgia Institute of Technology has applied it in an effort to make the IC global interconnects easier to design (Fig 2). Global interconnects are long lines running across the chip, and are the key to higher speed, according to many designers.
According to the Institute, higher speed cannot be achieved by merely increasing the cross-section of the global interconnects to lower resistance. This is because when clock frequency, cross-talk and interconnect area are considered, interconnect thickness and width are restricted to a specific design window.
As the rule drops from 0.18 to 0.05micron, it will become almost impossible to find a solution which satisfies demands imposed by clock frequency, cross-talk and interconnect area, says the Institute, which stresses the importance of 3D interconnect as a solution.
by Masahide Kimura
(September 2001 Issue, Nikkei Electronics Asia) |
