Dear Noel:
Did you ever take a look at how they did it? It is two pipelines 180 degrees out of phase like I stated before. It is technically incorrect to call it a 4GHz pipeline as no section runs at that speed, only 2GHz, 1.33GHz or worse.
Just think of it, by your lights, a section that runs at 1000MHz and one that runs at 1000MHz 0.1 cycle out of phase could be thought as a single 10GHZ pipeline because one uops could be followed by another after only 0.1 of a base cycle. By that reasoning, Athlon has a section that runs at infinite speed since two things occur at exactly the same time.
The scheduler of the P4 proves that there are 6 pipelines in the P4. 2 of them do the first half of the cycle uops and 2 of them do the last half of the cycle uops, one does loads and one does stores making a total of six. At one point in the last half cycle pipes, the uop goes through a stage 1.5 cycles long to line it up to the middle of the first half cycle pipe. Then the uop takes 1 cycle when scheduled. Later, the last half pipe goes through a 1.5 stage section to resychronize to the first half cycle pipeline for easier retirement (if they saved the room to duplicate all of the later stages and it shows as a single stage in the regular pipeline). Notice, at no time are the stages any shorter than 1 cycle. Thus, the double speed moniker, is not correct.
That was told in one of the white papers I read on the subject. The marketing people took a statement that it looks like part that uses half cycles may look like it runs at double speed, but that does not occur.
Pete |
