Government-Supported 50nm-Chip Project Starts
The Millennium Research for Advanced Information Technology (MIRAI) project in Japan has started to research and develop future semiconductor chips with 70-50nm design rule.
The project was jointly proposed by the Advanced Industrial Science and Technology (AIST) and the Association of Super-Advanced Electronics Technologies (ASET). Approval was given by the New Energy and Industrial Technology Development Organization (NEDO), a government organization, and 3.8 billion yen has been granted to the project.
The seven-year project is distinct from the Asuka project, which started in April and is concerned with 100-70nm SoC basic technology. The MIRAI (which means "future" in Japanese) includes five major projects, which are concerned with the development of 1) high-k material for a transistor gate insulator, 2) low-k material for interlayer dielectrics of multilevel metalization, 3) a new structured transistor, such as from strained silicon, 4) lithographic mask inspection technology, and 5) circuit architecture.
Compared with conventional consortium projects, the money provided by the government is not substantial. Today, advanced lithography equipment is priced at between 0.5 billion yen and 1 billion yen. The main research site will be the Tsukuba Super Clean Room, which is under construction on the premises of AIST, and is scheduled for completion in April 2002.
(October 2001 Issue, Nikkei Electronics Asia) |
