Andreas: The only thing that irritated me a little bit was Hans claim that the memory controller would not be integrated into the northbridge. I thought AMD had already confirmed that it would be integrated? (which could reduce latency significantly)
Apparently, this feature will be saved for the Sledgehammer (and be the main difference?).
It is something of a disappointment that the memory controller would not be integrated on-die for the regular (Claw)Hammer, as this would give a significant performance increase in all applications.
To be honest, I had expected ClawHammer to be much more Athlon-like, with the integrated memory controller and 64-bit'ness as the main differences, with a host of smaller changes including: changes to the cache structure (inclusive L1/L2, greater bandwidth, lower latency L2), SSE2, better prefetching, minor changes to the functional units, possibly increasing latency slightly where needed, so as not to limit the operating frequency, and lastly some tweaking of the balance betw. execution and decode resources.
By the looks of it, ClawHammer will be very different from Athlon, featuring a single-cycle latency L0 instruction cache, funky prefetching and speculation (and the equally funky forward collapse unit), etc. etc. etc.
-fyo |
