Pete, it is you who have terrible reading skills. Let me put up the quote that you used in order to illustrate your dotage.
"This dispatch bandwidth exceeds the front-end and retirement bandwidth, of three uops per clock, to allow for peak bursts of greater than 3 uops per clock and to allow higher flexibility in issuing uops to different dispatch ports."
You are noticing that the dispatch bandwidth exceeds the front end and retirement bandwidths, and you automatically assume that by conversive reasoning, the front end and retirement bandwidths are restricted, and thus unable to support the added bandwidth that the dispatch unit is given.
However, any moron willing to finish reading the sentence will understand Intel's reasoning for this. With the unpredictability of instruction streams, you don't ever really know what kind of traffic you can expect. The engineers for the Pentium 4 believed that it comes in bursts, and during those situations, extra bandwidth is required. Thus, extra bandwidth is given to the dispatch units, not subtracted from the front end or retirement units.
I don't know why you can't seem to understand this very simple concept. I'm sure it has something to do with your unwillingness to admit that there could be any good engineering inside an Intel microprocessor. You are obviously the one who's been benighted here.
So have a good day, and be sure not to forget your brainwashing mantras before you go to bed. I have no more interest in arguing with your nescience.
wanna_bmw |
