Combjelly, Re: "But so far, history has shown that it is harder to optimize the compilers than it is to throw transistors at the problem."
I have to disagree here. History has shown us that semiconductor manufacturers have thrown transistors at the problem, and up until now, things have worked out, but we are obviously hitting new walls, in terms of power dissipation (discussed at IPF), limits of ILP (also discussed during MPF), and system design challenges (again, discussed at IPF). Going the way of frequency directly affects power, EMI levels, system design levels, and others, while going the way of IPC increases die size, adds to thermal problems, and affects things in different ways.
Up until now, there hasn't been a lot of desire to use the compiler to increase CPU performance, but given that the old ways of increasing performance have become increasingly difficult, addressing the compiler is likely to be revisited. EPIC is not an inherently in-order design, although the first iteration is designed to operate this way. Future designs may incorporate some out-of-order principles, so that the best of both worlds can be achieved.
Additionally, changes within a compiler can be tested and implemented in real time. Software only needs to be recompiled to take affect. Hardware changes, on the other hand, require a long design and verification process that can easily last years. I think that this architecture shows a lot of promise, even though many people expected more the first time around. Fortunately, I see even the near future holding a lot of headroom for Itanium.
wanna_bmw |
