"What is taping out?"
"Taping out" means that the whole design has consistent
code that passes all RTL verification test cases,
that the silicon area was allocated for each block of
the design, that ground and power nets were designed,
the whole design was mapped onto manufacturing libraries,
linked to I/O pads/buffers, all routing was done within
manufacturing restrictions, reasonable clock tree was
generated that meet skew and load requirements, all
custom blocks (memories, I/O drivers, PLLs/Dlls) and
internal busses and top-level interconnect were placed and
successfully linked together, that the post-placing
and routing timing parameters were extracted back into
logical design, that those back-annotated codes with
timing constraints pass again all verification suits
and meet timing goals, that a check has been done that
no shorts has occurred between power rails in custom
blocks, that every driver has adequate strength
to drive corresponding net, that the power is properly
delivered into power-hungry areas, that heat dissipation
meets density goals, that ... what else did I forget?..
and the tool finally generates a set of files that
allows to build a set of photomasks. This means the
time to celebrate and nervously wait for first silicon
to arrive for bring-up and real testing.
Regards,
- Ali |
