Rambus introduces memory-interface technologies
By Andrew MacLellan
EBN
(10/22/01, 05:00:26 PM EST)
SAN JOSE -- Rambus Inc. today took the wraps off of two new memory-interface technologies aimed initially at boosting bandwidth in consumer and communications devices.
The technologies, which together comprise Rambus' new Yellowstone memory signaling architecture, are said to enable 3.2GHz data transfer rates in memory subsystems in applications like game consoles and communications line cards.
The memory technology, which is not yet in commercial use, could eventually find its way into the PC market, according to David Mooring, president of Rambus, Los Altos, Calif.
“There is room for radical changes to technology, and that's what we're doing with Yellowstone. We're taking the next great leap from the megahertz era to the gigahertz era,” Mooring said today at the Rambus Developer Forum here.
According to Rambus, Yellowstone is the first DRAM interface to include a phase-locked loop (PLL) and the first to employ differential signaling, features that the company said contribute to the performance advantage. Specifically, the architecture uses a pair of innovations: Octal Data Rate (ODR) operation and Differential Rambus Signal Levels (DRSL).
ODR is a follow on to the double- and quad-data-rate technology of earlier Rambus chips, such as the 800MHz Direct Rambus DRAM. The company increased the chip's internal data rate to 1.6GHz through the use of an on-board PLL then transferred the data on both the rising and falling edge of the internal clock to achieve a 3.2GHz data rate.
The use of DRSL drops voltage swings to 200mV, compared with 800mV for existing Direct RDRAM chips, and as high as 3.3V for DRAM using older LVTTL signaling technology.
“Minimizing the amplitude of these [voltage] swings is really the key to enabling us to reach this type of bandwidth,” said Rambus vice president Laura Fleming.
DRSL also continues Rambus' use of on-chip signal termination. The technique eliminates the expense and added real estate required by competing DRAMs that mount termination resistors on the printed-circuit board rather than directly on-chip, according to Mooring.
“In a consumer applications, this allows high performance at a low cost,” he said. “In communications applications, we can deliver the most performance possible out of a given pin count and form factor.”
Game machines in particular will benefit from the technology, given that market projections indicate bandwidth requirements in this sector increase 10 times every five years, Rambus said.
Speaking at the Rambus forum, Shin'ichi Okamoto, senior vice president and chief technology officer for Sony Computer Entertainment Inc., observed that the Sony PlayStation 2 offers 300 times the performance of its predecessor.
In communications applications like line cards, internal data processing requirements can be as high as two to four times the speed of the incoming data, because of the additional computational tasks performed by ASICs and on-board processors, Mooring said.
DRAM based on the Yellowstone technology could result in line-card memory subsystems using commercially available backplanes and connectors without resorting to more exotic optical components, he said.
To date, Rambus has announced no licensees for its Yellowstone technology. The company's road map doubles the architecture's data rate to 6.4GHz, though Rambus declined to say when this would occur. |
