Hammer musings.
Those slides where they trace through the pipleline stages on the Hammer make me curious. In particular, it looks as if they have the various major sections running on different clockrates. Either that, or stages of the pipeline are being executed in parallel. Or something. The slides show the first 12 stages completing in about a nanosecond. The next 8 take 4 more, but a fair amount of that time might be waiting on the L2 caches. Then 7 more nanoseconds is used for the 12 stages dealing with the main memory interface. A side note, the diagram seems to indicate that either an L2 access can be aborted on a miss, or maybe it is showing that a main memory access is overlapped with the L2 access, presumably that access is aborted if the data is in the L2. Hmm, I think it is the latter, but...
Anyway, either they are using a Hammer with a very high clock rate, 12GHz based on 12 stages completing in 1ns, or there is something funny going on. The next block of stages executes at 2GHz, and the final 12 stages execute at 0.583GHz. While I would believe that they might be running stages in parallel, there seems to be too much in the way of dependences in those stages to effectively do that. Now they may be do 6x pump on the early stages, but they'd need much faster transistors than I think they have to pull that off. Or maybe they are using asynchronous logic, but I am extremely dubious that anyone will be bringing something of this magnitude to market in that timeframe with asynchronous logic. So what does these stupid slides mean? |
