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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 214.780.0%9:53 AM EST
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To: combjelly who wrote (59814)10/24/2001 10:09:48 AM
From: pgerassiRead Replies (1) of 275872
 
Dear Combjelly:

Looking at the lines nest to the times you would notice that they start counting after the execute stage. Thus, 2 stages equal 1ns (L1 hit), 10 stages equal 5ns (L1 miss, L2 hit) and 22 stages equal 12ns (L2 miss, but not counting actual DRAM latency (for 1T CAS2 DDRDRAm is 9 cycles for a L2 cache line fill single channel (90s at PC1600, 67.5ns at PC2100 and 54ns at PC2700))). All stages are 0.5ns long or Hammer running at 2GHz (probable speed at 0.18u bulk).

Pete
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