SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 236.73-6.1%Jan 30 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: wanna_bmw who wrote (60548)10/26/2001 5:40:49 PM
From: jcholewaRead Replies (1) of 275872
 
> No, in some case, [MMX] latency is slower, but throughput
> is not. In fact, throughput is increased due to higher
> clock frequencies.
 
Nice try, but you're wrong here. The P4 can do a peak of half as many MMX ops per clock compared to Celeron. The workaround is SSE2, which equals per clock peak MMX op rate. But the cpu would have to be at double the frequency to be equal in peak MMX op rate of the Celeron.
 
 
 
> And how much of a penalty do you figure this causes?
> Do you have any data on the miss rate before and after the
> changes?
 
That doesn't matter. You made a blanket statement about P4 superiority, and I'm just gave you counterexamples. Suddenly you think that I'm trying to argue that the Celeron is faster than the P4, but that is not the case at all.
 
 
 
> The L2 cache is lower latency on the Pentium 4,
 
Assumptions! Do not apply assumptions without data!
 
cwi.nl
- L2 access (L1 miss) latencies look as follows:
miss-latency replace-time
PIII-Katmai 19 cycles 19 cycles
Athlon-Classic 19 cycles 19 cycles
PIII-Katmai-Xeon 15 cycles 15 cycles
Celeron-Mendocino 8 cycles 8 cycles
Duron 8 cycles 17 cycles
Athlon-Thunderbird 8 cycles 17 cycles
PIII-Coppermine 4 cycles 4 cycles
Pentium-4 24 cycles 16 cycles
 
Yes, could very well be tests in which the P4 has better latency than the Celeron. But there are tests (such as this one) in which the Celeron has better L2 latency than the P4 (and remember that the Celeron has the latency of the Coppermine, not the Mendocino). Intel's pdfs made claims that the P4 had one cycle better latency than the Coppermine, but that doesn't make it automatically true. It's just like the Thunderbird and it's "11 cycle" L2 latency (it wasn't, at least not all the time).
 
 
 
> Yes! You apparently do not fully understand the micro-architecture,
> which is why you are making these lame attempts to show that Intel's
> 5 year old P6 micro-architecture is somehow more advanced than their
> brand new Netburst micro-architecture. If you really knew all the
> changes that went into the Pentium 4, you would see that it is far
> more advanced, and is much more capable of higher performance
> than any P6 core, especially the Celeron.
 
By the gods!!! You're talking like a person who's been reading press quotes for all his life! You have no idea what we're talking about, do you? You made a very ignorant statement which shows that you are making blind assumptions, and I gave you counterexamples to show you that you cannot make assumptions like that! I did not make any assumptions here. I did not say that the Celeron is a more advanced processor. But you said not only that the P4 is more advanced, but that it is "far better equipped". This is a blanket statement, and I showed you several areas in which it is not better equipped for certain memory oriented activities (which is what many of these "future benchmarks" stress). And you have the audacity to refer to my statements of truth as "lame attempts"?
 
I am really disappointed at your treatment of honesty. Nothing I have said has been untrue. Everything from me that is speculation or query is clearly marked. You said "P4 IS better". I said "P4 MAY NOT BE better". You said "lame attempts".
 
Do you understand the difference between "may not be" and "isn't"? Do you not see how it is a bad thing to make decisions without having enough palpable data to back up what you are saying? Or do you think that counterexamples can only apply to other people?
 
BTW, miss rate applies to job size. If job size is under 8k, then the miss rate will be identical for both processors. If the job size is between 8k and 16k, then the P4 would be at a disadvantage. If the job size is larger than, say, 256K, then the P4 may start to have an advantage. Actually, due to a higher set associativity in its L2 cache, the kick-in benefit for the P4 may become higher than that.
 
 
 
> I don't blame you, but in the future, you will be very
> surprised with what the Netburst core can deliver.
 
If I do, it will be because I became surprised while analyzing the technical details. It won't be because I'm guessing on the weak, hole-filled data given to me by some random people who have preconceptions.
 
    -JC

PS: :p
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext