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Technology Stocks : Intel Corporation (INTC)

INTC 36.38

-1.3%

Dec 22 3:59 PM EST

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To: AK2004 who wrote (146631)	11/1/2001 5:44:45 PM
From: fingolfen	Read Replies (3) of 186894

I have read summary and it was unclear about definition of cost reduction. There are benefits in each of the two methodologies so it is hard to conclude which one is used by intel or industry. I've read the summaries too, and they really don't tie some of the slides together well. It's more clear if you watch the webcast as it includes the power-point presentation. One side shows the 0.13 micron ramp with 200mm dominating the effective wafer starts through 2002 and 300mm only starting to contribute heavily in 2003. A second slide shows the P3/P4 product mix which was P3 heavy this year, roughly 50/50 this quarter and becomes "essentially 100%" P4 by this time next year. Another slide shows relative proportions of 0.18 and 0.13 micron with 0.13 micron becoming the dominating technology in the Q3/Q4 time frame. It can be somewhat confusing I admit, but what Intel was reporting was an average die cost. Right now the vast majority of die are on 0.18 micron with roughly a 50/50 product mix. Next year the product mix becomes increasingly P4 rich (which we all know is much bigger than the P3). That would have the effect of increasing the average die cost. Competing against that effect is the transition to 0.13 micron. The Northwood (0.13 micron P4)die most likely as big (or maybe even a little bigger) than the coppermine (0.18 micron P3) die... yet Intel still projects a 7% average cost per die savings. By the end of 2003, only about 30% of the effective wafer starts will be on 300mm, yet the average cost per die has now dropped a total of 25%. Clearly Intel is getting huge cost savings going to 300mm. I therefore completely disagree with the analyst you quoted. His argument is incomplete and clearly based upon faulty assumptions. He did not understand the nature of data Intel was presenting, and rather than asking for clarification went off half-cocked and wrote an inaccurate assessment. The data the analyst thought he heard was 0.13 micron will reduce equivalent (not average) die costs 7% and 0.13 micron + 300mm will reduce equivalent die costs 25%. That is not what Intel presented in their webcast. Intel talked about an average cost per die which comprises two primary products (P3 and P4) on three different technologies (200mm 0.18 micron, 200mm 0.13 micron, and 300mm 0.13 micron). The cost savings was presented as a blended average rather than a cost savings per equivalent die. If the savings per equivalent die were presented, then the numbers would have looked better (i.e. 0.13 micron saves more than 7% per equivalent die and 300mm saves more than 18% per equivalent die), but would not have spoken to Intel's COG for the microprocessor division (which IMHO is a more useful number).

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